Drivers for data bus outputs of a typical CMOS VLSI semiconductor device use a bi-phase precharge/evaluate scheme for applying data to the bus. That is, the bus output is precharged to a voltage level substantially above ground prior to enabling data on the bus line. In this manner, the bus line capacitance is charged during the precharge phase to reduce the propagation delay during the evaluation phase.
In many applications, the precharge/evaluation cycle is governed by cyclical control signals such that precharging of the bus line occurs repeatedly whether or not data is subsequently applied to the line or is read by a receiving device. Consequently, a significant amount of power may be wasted during those cycles in which the bus line is not sampled. Furthermore, in places where the fanout and speed requirements of a bus are critical, the bi-phase precharge/evaluate scheme requires extensive latching and buffering, thereby increasing the device count, device sizes and the number of logic stages.
To overcome these disadvantages of cyclically precharging a data bus, schemes have been devised for precharging a bus line less frequently. For example, U.S. Pat. No. 4,983,860 discloses a data output buffer that is precharged under the control of a signal developed in an address transition detection circuit. U.S. Pat. No. 5,003,501 discloses a low power integrated circuit in which charging and discharging of a data bus occurs only when there is a data transition.
The present invention reduces power dissipation of a data bus driver by precharging the bus line only when necessary. Conventional bi-phase timing signals are retained; however, precharging of the data bus lines is performed only during the cycle prior to the one in which data sampling actually occurs. At all other times, a simple latch holds the data.